摘要
本设计对免缩放因子CORDIC算法进一步改进,改进包括进一步减少迭代次数和减少双步CORDIC算法中区间折叠模块输出调整方式。将改进后的算法与免缩放因子单步算法和免缩放因子双步算法相结合,给出一种正余弦波形产生的架构。用Verilog编写RTL级实现改进后的架构代码,仿真输出与Matlab数据对比,其中正余弦误差都集中在2%以下。在Altera EP2C70F89C6芯片上做FPGA验证,时钟频率可达1000MHz。
In this design, the CORDIC algorithm is further improved. The improvement includes reducing the number of iterations and reducing the output of the two-step CORDIC algorithm. Combining the improved algorithm with the un-sealed factor single-step algorithm and the un-scaled factor two-step algorithm, an architecture for the generation of sine and cosine waveforms is presented. Verilog RTL level to achieve improved architecture, simulation output and Matlab data comparison, which are cosine errors are concentrated in 2% or less. Altera EP2C70F89C6 chip FPGA verification, the clock frequency up to 1000MHz.
出处
《中国集成电路》
2017年第3期62-66,共5页
China lntegrated Circuit
