摘要
设计了一种集成数字内核和数模转换器(DAC)的高速、高分辨率直接数字频率合成器(DDFS)。其核心模块相幅转换器采用混合坐标旋转数字计算(CORDIC)算法,以缩短幅度计算的时钟周期,减少硬件消耗。DDFS电路采用多路并行结构,以降低核心运算模块的工作频率,采用多级交织采样实现低速信号到高速信号的采样,再将数据合成输出。DAC的设计采用温度计编码和二进制编码混合方式实现内部编码,采用双路归零编码方式实现信号输出。采用数字校准模块调整数字和模拟时钟的相位,确保信号从数字内核到DAC的正确采样。基于65 nm 1P8M CMOS工艺完成DDFS芯片的设计和流片,芯片面积为3.5 mm×4.7 mm。经测试在3.4 GHz的时钟频率下,输出信号频率约为1.36 GHz,窄带无杂散动态范围(SFDR)为89.75 dB;宽带SFDR为39.61 dB。
A high-speed and high-resolution direct digital frequency synthesizer(DDFS)which integrated the digital core and digital to analog converter(DAC)was designed.The hybrid coordinate rotation digital computer(CORDIC)algorithm was adopted in the core module phase-amplitude converter to reduce the clock cycle of the amplitude computation and hardware consumption.A multi-channel parallel structure was used in the DDFS to reduce the operating frequency of the core computing module,and the multi-stage interleaved sampling was used to achieve the sampling of low-speed signals to high-speed signals,and then the data were synthesized and output.The design of the DAC adopted a hybrid method of thermometer coding and binary coding to realize the internal coding,and a dual return-to-zero coding method was adopted to realize the signal output.A digital calibration module was used to adjust the phase of the digital and analog clocks to ensure the correct sampling of the signal from the digital core to the DAC.The DDFS chip with an area of 3.5 mm×4.7mm was designed and fabricated based on 65 nm 1P8M CMOS process.The measured narrowband spurious-free dynamic range(SFDR)is 89.75 dB and wideband SFDR is 39.61 dB with an output signal frequency of about 1.36 GHz at a clock frequency of 3.4 GHz.
作者
万书芹
于宗光
蒋颖丹
张涛
范晓捷
朱江
Wan Shuqin;Yu Zongguang;Jiang Yingdan;Zhang Tao;Fan Xiaojie;Zhu Jiang(The 58th Research Institute,CETC,Wuxi 214000,China)
出处
《半导体技术》
CAS
北大核心
2020年第6期419-424,共6页
Semiconductor Technology
基金
国家自然科学基金资助项目(61474092)。
