摘要
为了实现对高速输入数据的滤波,根据FIR(有限冲激响应)数字滤波器并行设计思想,在脉动阵列FIR数字滤波器的基础上,经过认真设计,提出了一种基于FPGA(现场可编程门阵列)的高速FIR数字滤波器的设计方法。以一个l6阶FIR数字滤波器的设计为例,在FPGA上用VHDL语言实现了这种设计方法。在Modelsim下仿真表明这一方法是可行的,可支持高达1 GSPS(10亿次采样每秒)的输入数据。
To realize filtering of high-speed input data, and aiming at the design method of systolic FIR digital filter, this paper proposes a design method of high-speed FIR filter based on FPGA. The implementation of this design is illustrated by the process of designing a 16-tap FIR digital filter using VHDL language. Simulation by Modelsim shows that the design is feasible and can support high-speed data of 1 GSPS.
出处
《信息化研究》
2009年第4期26-28,共3页
INFORMATIZATION RESEARCH
