摘要
为了整合串行、并行、拆分查找表三种主要分布式算法在存储器占用和时钟周期利用上的优缺点,提出了一种利用并行+拆分查找表分布式算法实现高阶FIR滤波器的方法。对分布式算法的串行、并行和拆分查找表结构进行比较说明,通过分析计算,阐述了新提出的并行+拆分查找表分布式算法的优势。介绍了以FPGA为核心器件及其他国产元器件搭建实现的系统硬件电路,元器件国产化率高达100%。同时,利用Matlab软件进行理论仿真,最后应用网络分析仪测试高阶FIR滤波器的幅频特性,验证了该算法的有效性和实时性。
In order to integrate the advantages and disadvantages of the three main distributed algorithms(DA)of serial,parallel,and splitting look-up-table in memory occupation and clock cycle utilization,a new structure of high-order finite impulse response(FIR)filter based on parallel+splitting look-up-table DA is presented.After comparison of series DA,parallel DA,and splitting look-up-table DA,the advantages of parallel+splitting look-up-table DA are explained.Through analysis and calculation,the advantages of the newly proposed parallel+splitting look-up-table distributed algorithm are explained.The implementation of system hardware circuits with FPGA as the core device and other domestic components is introduced.The localization rate of components is as high as 100%.Simultaneously,Matlab software is used for theoretical simulation.Finally,amplitude frequency characteristic of high-order FIR filter is tested by network analyzer.The effectiveness and real-time performance of the algorithm are verified.
作者
柴乾隆
CHAI Qian-long(College of Aviation Mechanical and Electronic Engineering,A VIC Lanzhou Wanli Aviation Electromechanical Co.,Id,Lanzhou 730070,China)
出处
《测控技术》
2021年第6期85-89,99,共6页
Measurement & Control Technology
关键词
FPGA
FIR滤波器
查找表
幅频特性
FPGA
FIR filter
look-up-table
amplitude frequency characteristic
