摘要
分析了数字下变频的原理,设计实现了能进行1、2、4、8等可选抽取倍数的高速数字下变频系统。对系统中的混频器和滤波器进行了优化设计。采用基4布斯编码和4-2压缩器,缩短混频器中的关键路径;引入基于Horner法则和子表达式共享的正则有符号数(CSD)编码,减小滤波器的硬件消耗。设计的数字下变频系统用于四通道、560 MHz 14位时间交织模数转换器(TIADC),并基于FPGA完成功能验证。结果表明,当输入信号频率为380 MHz、抽取倍数为8时,I/Q两路信号的无杂散动态范围(SFDR)在90 dB以上。
A high speed DDC system with 1, 2, 4, or 8 times optional decimation ratio was designed by analyzing the principle of the common digital down converter system. The mixers and filters of the system were optimized. A radix-4 Booth encoder and a 4-2 compressor were used in the mixers to shorten the critical path. A CSD coding based on the sharing of sub-expressions and Horner rule was utilized at the filters to reduce the hardware consumption. The digital down-conversion system was designed for a four-channel 560 MHz 14-bit time-interleaved analog-to-digital converter(TIADC), and the function verification was completed based on FPGA. The results showed that the SFDR of the I/Q signals was above 90 dB when the input signal frequency was 380 MHz and the decimation ratio was 8.
作者
王舰
陈红梅
张昊哲
王兰雨
尹勇生
WANG Jian;CHEN Hongmei;ZHANG Haozhe;WANG Lanyu;YIN Yongsheng(Institute of VLSI Design,Hefei University of Technology,Hefei 230601,P.R.China;IC Design Web-Cooperation Research Center of MOE,Hefei University of Technology,Hefei 230601,P.R.China)
出处
《微电子学》
CAS
北大核心
2022年第3期418-424,共7页
Microelectronics
基金
安徽省科技攻关计划项目(202104g01020008)
国家自然科学基金资助项目(61704043)
模拟集成电路国家级重点实验室基金资助项目(6142802190506)。
关键词
数字下变频
半带滤波器
混频器
高速数据采集
digital down converter
half-band filter
mixer
high speed data acquisition
