摘要
以一种适用于现场可编程门阵列(FPGA)芯片的宽频率范围电荷泵锁相环(CPPLL)为例,介绍了一种通过添加简单辅助电路来减小锁相环(PLL)上电锁定时间的方法。该方法在传统电荷泵锁相环的基础上添加了预充电电路,可以大大减少压控振荡器控制电压(VCTRL)拉升的时间。除此之外还添加了频率比较电路,将较宽的频率范围分成若干个窄频率区间,并用窄频率区间的中心频率来作为关断预充电电流的判定频率,这样就可以在不影响PLL正常功能的情况下均衡宽频率范围锁相环各频率下的上电锁定时间。基于28 nm工艺,对添加了辅助电路的PLL进行spectre仿真验证,在频率范围为800~1600 MHz时,上电锁定时间为1.68~2.29μs。
Taking a wide frequency range charge pump phase locked loop(CPPLL)for field programmable gate array chip as an example,this paper introduces a method to reduce the power on lock time by adding a simple auxiliary circuit.This method adds a precharge circuit to the traditional charge pump phase locked loop,which can greatly reduce the time of VCTRL voltage rising.In addition,a frequency comparison circuit is added to divide the wide frequency range into several narrow frequency intervals,and the center frequency of the narrow frequency range is used as the judging frequency to turn off the precharge current,so that the power on lock time of wide frequency range phase locked loop can be balanced without affecting the normal function of phase locked loop.In this case,based on 28 nm process,after spectre simulation,when the frequency of phase locked loop with auxiliary circuit is 800-1600 MHz,the power on lock time is only 1.68-2.29μs.
作者
王德龙
刘彤
WANG Delong;LIU Tong(East Technologies Inc.,Wuxi 214072,China)
出处
《电子与封装》
2021年第2期80-84,共5页
Electronics & Packaging
关键词
锁相环
电荷泵锁相环
锁定时间
频率比较
phase locked loop
charge pump phase locked loop
lock time
frequency comparison
