摘要
文中描述了一种自偏置型锁相环电路,通过采用环路自适应的方法得到一个固定的阻尼系数ξ以及带宽和输入频率的比值ωN/ωREF,从而保证环路的稳定。传统锁相环电路设计需要一个固定的电荷泵充放电电流和固定的VCO增益,这样才能保持系统的稳定性。但是当工艺发展到深亚微米尤其是65 nm以下的时候,芯片的供电电压都在1 V以下且器件的二级效应趋于严重,此时要得到一个固定的电流值或者固定的VCO增益是很困难的。自偏置锁相环解决了这个问题,由于采用了自适应环路的设计方法,使得系统受工艺、温度和电压的影响非常小,而且锁定范围更大。可以广泛应用于时钟发生器以及通信系统。芯片采用SMIC标准低漏电55 nm CMOS工艺制造,测试均方抖动为3.8 ps,峰-峰值抖动25 ps。
This paper describes a self-biased Phase locked loop circuit （PLL）, by using a loop adaptive method to obtain a fixed damping factor ξ and a constant loop dynamics. In general, conventional PLL circuit design requires a fixed charge pump current and a fixed gain of VCO to maintain loop stability. However, when the process development to the deep sub-micron especially below 65 nm and the supply voltage of the chip are below 1 V, the secondary effects of the device tends to be severe. It is difficult to obtain a fixed current value or a fixed VCO gain. This paper presents a solution that using the adaptive loop to get a wide locking range and make the influence of the system by the process, temperature and voltage independent. It is widely used in such as the clock generator and communication system. This chip was fabricated in SMIC standard low-leakage 55 nm CMOS process. The test result shows JRMS of 3.8 ps, JPK-PK jitter of 25 ps, respectively.
出处
《电子与封装》
2013年第2期14-16,27,共4页
Electronics & Packaging
