摘要
提出一种SCL结构差分型鉴频鉴相器(PFD),这种鉴频鉴相器能大幅度降低鉴相死区,而且具有噪声低、速度快等优点.这种差分型PFD在高速、低抖动、低噪声PLL中有着广泛的应用.该电路基于chartered 0.35μm CMOS工艺,并用MENTOR eldo进行仿真,仿真结构表明,该PFD死区只有0.03ns.并且可以大大降低VCO控制电压的波纹.
A new differential-type phase frequency detector based on SCL structure is presented. The detector can greatly reduce the dead-zone phenomenon in phase characteristic and has the feature of low noise、high speed. The presented PFD can be widely used in high speed,low jitter and low noise PLLs. The circuit is simulated by MENTOR ELDO with the chartered 0.35μm CMOS technology. The simulation indicates that the presented PFD has a dead-zone less than 0.03ns,and the ripple of the VCO control line can be greatly reduced.
出处
《电脑知识与技术（过刊）》
2007年第20期476-478,共3页
Computer Knowledge and Technology
基金
安徽省教育厅自然科学研究重点项目(2006kj012a)
