摘要
为满足网络安全认证的需求,提出了一种高吞吐率的国密SM3的硬件IP核的设计方法。该方法用3级流水线缩短了每轮运算的关键路径,提升了系统时钟,并将64轮运算全部展开,实现轮间64级流水线,总共192级的全流水线设计,能够同时实现192组消息的SM3运算。基于SMIC 0.18μm的工艺,实现了该IP核,时钟频率达到了200 MHz,吞吐率达到了102.4 Gbit/s,比现有的研究成果提升39.3%。
In order to meet the need of internet security authentication,a high throughput rate SM3 IP design method is proposed.This method adopts 3-stage pipeline in the SM3 round calculation and shorts the critical path and thus increases the system clock frequency,and expands the 64 rounds calculation with 64-stage inter-round pipeline,which gets a total 192-stage pipeline,and makes it possible for 192 messages do the SM3 at the same time.This IP has been implemented on the SMIC 0.18μm process,and got the result with a 102.4 Gbit/s throughput rate when the clock is 200 MHz,which is 39.3%faster than other research result.
出处
《电子器件》
CAS
北大核心
2017年第3期622-625,共4页
Chinese Journal of Electron Devices
基金
国家自然科学基金青年项目(11605030)
贵州省联合基金项目(黔科合J字LKG[2013]40号)
贵州省联合基金项目(黔科合J字LKG[2013]41号)
