摘要
为降低芯片功耗,提升性能,从系统级、结构级和RTL级3个层次提出了一种片上系统(System on Chip,SoC)芯片的低功耗设计方法,并在样片中得以验证。在系统级层面,根据SoC芯片的不同工作场合,在正常运行模式的基础之上,设计了睡眠、停止和待机3种低功耗模式。在结构级层面,将整个芯片划分为VDD、VDDA和VBAT3个电压域,以降低系统功耗。在RTL级,针对不同的模式切换,设计了时钟管理技术,实现了对不同模式下不同时钟的控制。仿真和实验结果证明了设计的合理性,实测数据表明,睡眠模式最多降低59.1%的功耗,停止和待机模式降低了3~4个数量级。
For the sake of reducing power consumption and improving system performance, an low power design method for S o C is presented in this paper in the views of system level, structure level and R T L level which has been confirmed in an example wafer. Taking various working conditions into consideration, the sleep mode and standby m o d e are designed according to operating principle in run m o d e. In order to optimize power consumption^ this whole system power is provided b y 3 kindof voltages, Vdd , Vdda and Vbat. Besides, a clock management technology is proposed to accomplish switch of different clocks a m ong various modes in R T L level. The simulation and experiment results shows that the power-consume in low power mode is decreased 59.1% at most. In addition, the consumptions in stop m o d e and standby m o d e are reduced about 3~4 order of magnitude.
出处
《电子与封装》
2018年第2期40-45,共6页
Electronics & Packaging
