摘要
随着半导体工艺水平的不断发展,3D芯片技术已成为一大研究热点。"绑定中测试"环节的提出对于芯片的测试流程有了新的要求。但是,"绑定中测试""一绑一测"的特点会使部分裸片被重复测试,从而带来测试时间的增加。从"绑定中测试"的过程出发,协同考虑测试功耗与"理论制造成本"对于"绑定中测试"的影响,提出"多绑一测"的测试流程。在此基础上提出相应的广度优先遍历算法,结合ITC’02电路的相关参数,体现本文思想在实际生产制造中的现实意义。
With the continuous development of semiconductor technology, 3D chip technology has become a hot research highlight, and the process of chip testing has a new requirement for ＂mid-bond tests＂. But for the ＂mid-bond test＂, ＂one testing after every bonding＂ makes some dies repeat testing, thus resulting in an increase of test time. We put forward a ＂one testing after multiple bondings testing process which considers the effect of test power consumption and ＂theoretical manufacturing cost. Besides, we also introduce a breadth first traversal algorithm, which combines the relevant parameters of ITC02 circuit. The combination reflects our proposal＇s practical significance in actual production.
出处
《计算机工程与科学》
CSCD
北大核心
2016年第8期1602-1608,共7页
Computer Engineering & Science
基金
国家自然科学基金重点项目(61432004)
国家自然科学基金(61474035
61204046
61306049)
安徽省科技攻关项目(1206c0805039)
安徽省自然科学基金(1508085QF129)
教育部新教师基金(20130111120030)
关键词
绑定中测试
多绑一测
功耗约束
“理论制造成本”约束
mid-bond test one testing after multiple bondings^power constrains theoretical manufacturing cost constrains
