摘要
提出了一种功耗约束下的三维堆叠集成电路(3D-SICs)测试调度优化算法。该算法在功耗约束下,协同优化了测试应用时间、TAM总线带宽和测试硬件开销。通过采用ITC’02标准电路中的d695和p93791做应用验证,结果表明该算法将测试应用时间分别减少为91.25%和93.11%,证明算法能有效地减少测试应用时间,降低测试成本。
This paper presented a test scheduling optimization algorithm for 3D stacked ICs under power constrains ,which op- timized test application time, TAM bus bandwidth and hardware expenses collaboratively.Using d695 and p93791 of the benchmark circuits ITC＇02 to verify, the experimental results show that the test application time is reduced to 91.25% and 93.11% respectively. It proves that the proposed algorithm can effectively reduce the test application time and the test cost.
出处
《仪表技术与传感器》
CSCD
北大核心
2015年第2期91-93,共3页
Instrument Technique and Sensor
基金
湖南省科技厅科技计划项目(2013FJ3077)
湖南省教育厅资助科研项目(12C1084)
衡阳市科技计划项目(2012KJ31)
湖南省"十二五"重点建设学科资助项目(湘教发[2011]76号)
