摘要
将电源电压降低到晶体管阈值电压附近可以有效提高数字电路的能效,而近阈值标准单元库是近阈值数字电路设计的基础。通过分析逻辑门间静态噪声容限的兼容性、逻辑门在宽电压范围下延时变化情况,并通过求解最大包问题等的相关算法,对现有的商用数字CMOS标准单元库进行有效筛选,得到适用于低电压工作的近阈值数字CMOS标准单元库。通过一个应用于传感网中的双电压域、双核微控制器流片测试,对此标准单元库进行了验证,结果显示其中工作在0.5 V下的高能效核的能量效率相较传统工作电压下提高到2.76倍。
Lowering the supply voltage to the transistor threshold region can improve the power efficiency of the digital circuit. Near-threshold standard cell library is the basis of the near-threshold digital circuit design. To establish the near-threshold CMOS library working in low voltage,a filtering method for the commercial normal voltage digital CMOS standard cell library was proposed by analyzing the compatibility of static noise margin of the connected logic gates and the delay variation in the operation voltage range,and solving the maximum clique problem and related problems. A dual-voltage dual-core microcontroller test chip was taped out to validate the library. The result shows that the high energy efficiency core under 0. 5 V supply voltage has a 2. 76 times energy efficiency improvement compared to that under the normal supply voltage.
出处
《半导体技术》
CAS
CSCD
北大核心
2015年第12期889-893,915,共6页
Semiconductor Technology
基金
国家自然科学基金资助项目(61271269)
国家高技术研究发展计划(863计划)资助项目(2013AA01320)
北京市青年英才计划资助项目(YETP0102)
关键词
近阈值电路
数字电路
标准单元
静态噪声容限
传感网
near threshold circuit
digital circuit
standard cell
static noise margin
sensor network
