摘要
对一种具有倾斜表面漂移区SOI LDMOS的制造方法进行了研究,提出采用多窗口LOCOS法形成倾斜表面漂移区的新技术;建立了倾斜表面轮廓函数的数学模型,并开发了用于优化窗口尺寸和位置的计算机程序。TCAD 2-D工艺仿真验证了该技术的可行性。设计了漂移区长度约为15μm的SOI LDMOS。数值仿真结果表明,与RESURF结构器件相比较,其漂移区电场近似为理想的常数分布,并且击穿电压提高约8%,漂移区浓度提高约127%。由此可见,VLT是一种理想的横向耐压技术。
A novel fabrication method for SO1 LDMOS with gradient surface in drift region was proposed. In this process, drift region with graded thickness was formed by using a multi-slit LOCOS approach. A mathematic model was derived for gradient surface profile, and a computer program was developed to optimize the slit size and location. The model and program were validated by 2-D process simulation with TCAD. SOI LDMOS with 15μm long drift region was designed. Simulation results showed that, compared to RESURF device, the novel device had a constant electric field in the drift region, which led to an improvement of 8% in breakdown voltage; and an increase of 127% in doping concentration of the drift region.
出处
《微电子学》
CAS
CSCD
北大核心
2010年第2期300-304,共5页
Microelectronics
基金
国家自然科学基金资助项目(60806027)
江苏省自然科学基金资助项目(BK2007605)
电子薄膜与集成器件国家重点实验室开放基金资助项目(KF2008001)
南通市科技项目(K2008016)
