摘要
提出了一种新的高速加法器电路.该加法器采用混合握手协议,将超前进位与异步自定时技术相结合,根据进位链出现的概率大小来分配进位路径,可以在保持异步结构低功耗的同时提高运算速度.仿真结果表明,在SMIC 0.18μm工艺下,32位异步超前进位加法器平均运算完成时间为0.880932 ns,其速度是同步串行加法器的7.33倍,是异步串行加法器的1.364倍和异步进位选择加法器的1.123倍,且电路面积和功耗开销小于异步进位选择加法器.
A new adder design is proposed. Combining CLA and asynchronous self-timed techniques,the adder introduces the hybrid handshake protocol and distributes the carry-generating path with the probabilities of the carry chains. It can speed up the asynchronous adder while keeping a low power and area cost. The adder implements the 0.18μm technique of SMIC. Simulation result shows that the 32-bit asynchronous parallel adder achieves the average delay of 0. 880 932 ns. Its speed is 7.33 times faster than the synchronous ripple adder, 1. 364 times faster than the asynchronous ripple adder, and 1. 123 times faster than the asynchronous carry-select adder. And its area and power cost are less than those of the asynchronous carry-select adder.
出处
《西安电子科技大学学报》
EI
CAS
CSCD
北大核心
2009年第1期33-37,共5页
Journal of Xidian University
基金
国家自然科学基金资助(90407016
60676009)
关键词
异步
并行
超前进位
加法器
自定时
asynchronous
parallel
carry-look-ahead
adder
self-timed
