摘要
随着半导体工艺的发展,片上系统(System-on-Chip,SoC)内部集成的不同功能IP(Intellectual Property)核越来越多。各IP核通过总线方式连接,多核同时抢占总线很大地制约了片上系统的性能。高效的总线仲裁器可以解决多核抢占总线引起的冲突和竞争问题,提升片上系统性能。该文提出一种改进的高速彩票总线仲裁器。使用4相双轨协议代替时钟实现彩票抽取机制以防止彩票丢弃,采用异步流水线交叉并行的工作方式以提升工作速度。在NINP(NonIdling and NonPreemptive)模型下通过65 nm CMOS工艺的Xilinx Virtex5板级验证,相比经典彩票仲裁器和动态自适应彩票仲裁器,具有更好的带宽分配功能,有效避免"撑死"和"饿死"现象,工作速度提高49.2%以上,具有一定的功耗优势,适用于有速度要求的多核片上系统。
With the development of semiconductor technology, integration of an increasing number of IP（Intellectual Properties） cores into a single SoC（System-on-Chip） becomes feasible. The IP cores are connected via a bus, thus the preemption of bus among IP cores degrades the performance of SoC. Efficient bus arbiters can deal with the contentions and conflicts caused by the preemption of bus, and in this way the performance of SoC is improved. An improved high-speed lottery bus arbiter is proposed. The lottery decision mechanism deploys four-phase dual-rail protocol rather than clock to avoid the loss of tickets, and it utilizes cross parallel working manner of asynchronous pipeline to improve the working speed. In the NINP（NonIdling and NonPreemptive） model, simulations and verifications are made on Xilinx Virtex5 of 65 nm CMOS. The results show that compared with the commonly-used lottery arbiter and adaptive dynamic lottery arbiter, the proposed arbiter is better in output bandwidth allocation and can avoid ＂starvation＂ and ＂monopolization＂ of bus. Furthermore, the working speed increases by over 49.2% and it has advantages in power consumption. Thus it can be applied to multi-core SoC, which has requirements in working speed.
出处
《电子与信息学报》
EI
CSCD
北大核心
2014年第8期2016-2022,共7页
Journal of Electronics & Information Technology
基金
国家自然科学基金(60725415
61172030)资助课题
