摘要
目的开发一种新型的高速低功耗加法器设计方案。以满足SOC对高速低功耗运算的需要。方法采用中国算盘算法,接口采用异步双轨握手协议,将算盘加法与异步自定时技术相结合,减少运算的进位产生,提高运算并行度。结果提出了一种新的高速加法器电路。测试结果表明,在SMIC 0.18μm工艺下,32位异步算盘加法器平均运算完成时间为0.957ns,其速度是同步串行加法器的6.747倍,是异步串行加法器的1.517倍和异步进位选择加法器的1.033倍。且电路平均功耗只有异步进位选择加法器的25%。结论中国算盘算法与异步自定时电路相结合的加法器电路,有很好的速度和功耗特性,有很广阔的应用和研究前景。
Aim To develop a new high speed and low power adder design scheme for the demand of high speed and low power computing in SOC. Methods A new adder design is proposed in this paper. The adder adopts the Chinese abacus algorithm, combined with asynchronous self-timed techniques, and it also introduces the hybrid handshake protocol in the scheme. It can decrease the number of the carries and increase the parallel computing degrees. So it can achieve high speed while maintaining low power. Results The adder implemented the 0. 18μm technique of SMIC. The test result shows the 32-bit asynchronous parallel adder achieves the average computation duration is 0.957ns. Its speed is 7.33 times faster than the synchronous ripple adder, 1. 517 times faster than the a- synchronous ripple adder, and 1. 033 times faster than the asynchronous carry-select adder. And its average power is only 25% of the asynchronous carry-select adder. Conclusion The adder design which combine with Chinese abacus algorithm and asynchronous self-timed techniques has good performance on high speed and low power. It has wide implement and develop prospective.
出处
《西北大学学报（自然科学版）》
CAS
CSCD
北大核心
2011年第4期606-610,共5页
Journal of Northwest University（Natural Science Edition）
基金
国家自然科学基金资助项目(90407016
60676009)
关键词
异步
算盘
加法器
自定时
asynchronous
abacus
adder
self-timed
