期刊文献+

剪切蠕变下无铅焊点厚度的尺寸效应 被引量:5

Size effects of lead-free solder joints thickness under shear creep
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摘要 利用自制的电子测试系统,测量分析了试样焊点厚度(0.05~0.50mm)对电阻应变的影响。结果表明:在剪切蠕变条件下,焊点厚度为0.25mm时,电阻应变最小,蠕变寿命最长。利用有限元软件ANSYS对焊点的蠕变应变进行仿真分析。结果显示:随着焊点厚度变化,焊点蠕变应变的变化趋势与实验结果一致。将相同厚度下的电阻应变与蠕变应变进行拟合,得到了电阻应变与蠕变应变之间的定量关系式。 The resistance strain of solder joints with different thickness (0.05-0.50 mm) were measured by a self-made apparatus. The results show that the solder joints with 0.25 mm thickness yield minimum resistance strain and the longest creep life. Creep strain of the solder joints were simulately analysed by finite element method (FEM). The results show that FEM simulate analyses of the creep strain of solder joints present the same change trend as the experimental results when the solder joints' thickness changes. The quantificational relationships between resistance strain, creep strain and solder joints thickness were obtained according to the experimental data and the between creep strain and resistance strain was obtained FEM data, respectively. Finally, the quantificational relationship between creep strain and resistance strain was obtained.
出处 《电子元件与材料》 CAS CSCD 北大核心 2008年第8期55-58,共4页 Electronic Components And Materials
基金 国家自然科学基金资助项目(No.50376076)
关键词 电子技术 无铅焊点 尺寸效应 厚度 电阻应变 electron technology lead free solder joint size effect thickness resistance strain
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参考文献16

  • 1Kawai S, Nishimura A, Hattori T, et al. Reliability evaluation of electronic devices [J]. Mater Sci Eng., 1991, A143:247-256. 被引量:1
  • 2Kamei T, Nakamura M. Hybrid IC structures using solder reflow technology [J]. Microelectron Reliab, 1980, 20(3): 388. 被引量:1
  • 3Hall P M. Solder post attachment of ceramic chip carriers to ceramic film integrated circuits [J]. Microelectron J, 1983, 14(5): 81. 被引量:1
  • 4Goldman L S. Geometric optimization of controlled collapse interconnections [J]. IBM J Res Devel, 1969, 13(3): 251-265. 被引量:1
  • 5Satoh R, Ohshima M, Komura H, et al. Development of a new micro solder bonding method for VLSI [J]. Int Electron Packg Soc Inc, 1983, 455-461. 被引量:1
  • 6Nagesh V K. Reliability of flip chip solder bump joints [J]. Microelectron Reliab, 1983, 23(3): 588. 被引量:1
  • 7Goldman L S, Totta P A. Area array solder interconnection for VLSI [J]. Solid State Technol, 1983, 26(6): 91-97. 被引量:1
  • 8Howard R T. Optimization of indium lead alloys for controlled collapse chip connection application [J]. IBM J Res Devel, 1982, 26(3): 372-389. 被引量:1
  • 9Matsui N, Sasaki S, Ohsak T. VLSI chip interconnection technology using stacked solder bumps [J]. Microelectron Reliab, 1989, 29(4): 1989. 被引量:1
  • 10吴懿平,崔昆,张乐福.焊膏厚度对CBGA组装板可靠性的影响[J].电子工艺技术,2000,21(4):153-156. 被引量:9

二级参考文献10

  • 1和平,彭瑶玮,乌健波,孟宣华,何国伟.vf-BGA封装焊球热疲劳可靠性的研究[J].Journal of Semiconductors,2004,25(7):874-878. 被引量:6
  • 2许杨剑,刘勇,梁利华,余丹铭.芯片封装焊球连接疲劳寿命预测分析——能量法和有效应变法之比较[J].应用力学学报,2005,22(2):279-284. 被引量:2
  • 3Lee W W,Nguyen L T,Selvaduray G S. Solder joint fatigue models:review and applicability to chip scale package. Microelectron Reliab, 2000,40 : 231 被引量:1
  • 4Darveaux R. Effect of simulation methodology on solder joint crack growth correlation. Proceedings of 50th Electronic Components and Technology Conference , 2000 :1048 被引量:1
  • 5Zahn B A. Finite element based solder joint fatigue life predictions for a same die size-stacked-chip scale-ball grid array package. Proceedings of SEMI/IEEE International Electronics Manufacturing Technology Symposium, 2002:274 被引量:1
  • 6LaU P,Islam M N,Singh N,et al. Model for BGA and CSP reliability in automotive underhood applications. IEEE Transactions on Components and Packaging Technologies,2004,27(3):585 被引量:1
  • 7Chen X,Chen G, Sakane M. Prediction of stress-strain relationship with an improved Anand constitutive model for lead-free solder Sn-3.5Ag. IEEE Transactions on Components and Packaging Technologies,2005,28(1) :111 被引量:1
  • 8Lau J H,Lee S W R. Modeling and analysis of 96. 5Sn-3.5Ag lead-free solder joints of wafer level chip scale package on buildup microvia printed circuit board. IEEE Transactions on Electronics Packaging Manufacturing,2002,25(1):51 被引量:1
  • 9Ase Kaohsiung. CSP VFBGA. 2005. http: ff www. asetwn.com. tw/content/2-4-1, html. Cited 20 Jan 2006 被引量:1
  • 10吴懿平,张乐福,崔昆.焊盘尺寸对PBGA组装板可靠性的影响[J].电子工艺技术,1999,20(4):153-156. 被引量:5

共引文献15

同被引文献68

  • 1王建华,孟工戈,孙凤莲.SAC305/Cu微焊点界面金属间化合物生长速率[J].焊接学报,2015,36(5):47-50. 被引量:10
  • 2ZIMPRICH P, BETZWAR-KOTAS A, KHATIBI G, et al. Size effect in small sealed lead-free solder joints [J]. J Mater Sci: Mater Electron, 2008, 19(4): 383-388. 被引量:1
  • 3CUGNONI J, BOTSIS J, SIVASUBRAMANIAM V, et al. Experimental and numerical studies on size and constraining effects in lead-free solder joints [J]. Fatigue Fraet Eng Mater Struet, 2006, 30(5): 387-399. 被引量:1
  • 4CUGNONI J, BOTSIS J, JANCZAK-RUSCH J. Size and constraining effects in lead-free solder joints [J]. Adv Eng Mater, 2006, 8(3): 184-191. 被引量:1
  • 5PLUMBRIDGE W J. Solders in electronics [J]. J Mater Sei, 1996(3): 2501-2514. 被引量:1
  • 6KIM K S, HUH S H, SUGANUMA K. Effect of fourth alloying additive on microstructures and tensile properties of Sn-Ag-Cu alloy and joints with Cu [J]. Microelectron Reliab, 2003, 43(2): 259-267. 被引量:1
  • 7SHARIF A, CHAN Y C, ISLAM R A. Effect of volume in interracial reaction between eutectie Sn-Pb solder and Cu metallization in microelectronic packaging [J]. Mater Sci Eng B, 2004. 106(2): 120-125. 被引量:1
  • 8Tong Q. Recent advances on a wafer-level flip chip packaging process[C]. IEEE ECTC 50th Symp, 2000: 101-106. 被引量:1
  • 9Vianco P T. Lead-Free Solder Interconnection Reliability[M]. Detroit: ASM International, 2005. 被引量:1
  • 10Morris J W, Goldsein J L F, Mei Z. Microstructure and Mechanical Propertiesof Sn-In and Sn-Bi solders[J]. Journal of Electronic Materials. 1993, 22(7): 25-27. 被引量:1

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