摘要
提出了一种简化的抗零值差分功耗分析的先进密码算法(AES)及其VLSI实现方案。为了降低抗攻击技术对原有运算单元速度面积的影响,在分析原改进的AES算法的基础上,提出了更为简单的加法性屏蔽算法,并用复用相应模块、优化运算次序等方法实现了以极小的硬件代价获得很高的抗攻击性能。设计采用HHNEC 0.25μm标准CMOS工艺,单元面积约43k等效门。在40MHz工作频率下,128-bit加密的数据吞吐率达到470Mb/s。
This paper proposes a simplified AES algorithm of resistant to zero value DPA （differential power analysis） attack and its VLSI implementation. In order to minimize the influence of the modification to the hardware, it makes some improvements to the additive masking AES algorithm and employs such methods as module reuse and altering calculation order to reduce chip area and maintain its speed. Using the HHNEC 0.25pro CMOS process, the scale of the design is about 43k equivalent gates and its system frequency will be up to 40MHz. The throughputs of the 128-bit dada encryption and decryption are as high as 470Mb/s.
出处
《计算机工程》
CAS
CSCD
北大核心
2007年第16期220-222,233,共4页
Computer Engineering
基金
国家自然科学基金资助项目(90407002
60576024)
