摘要
提出了一种抗差分功耗分析和差分故障分析的AES算法硬件设计与实现方案,该设计主要采用了数据屏蔽和二维奇偶校验方法相结合的防御措施。在保证硬件安全性的前提下,采用将128bit运算分成4次32bit运算、模块复用、优化运算次序等方法降低了硬件实现成本,同时使用3级流水线结构提高了硬件实现的速度和吞吐率。基于以上技术设计的AESIP核不仅具有抗双重旁道攻击的能力,而且拥有合理的硬件成本和运算性能。
A VLSI implementation of AES algorithm against both differential power attack and differential fault attack was proposed. The main countermeasures employed in this hardware design are masking technique and two-dimensional parity-based concurrent error detection method. And exploits such methods as separating 128bit calculation into four 32bit calculations, module reuse and optimization of calculation order was exploited to reduce hardware cost. Moreover, a 3 level pipelined structure of AES encryption and decryption is used to improve hardware speed and throughput. The AES IP core based on these techniques can resist two kinds of side channel attacks with reasonable performance and cost.
出处
《通信学报》
EI
CSCD
北大核心
2010年第1期20-29,共10页
Journal on Communications
基金
国家自然科学基金资助项目(60776028)~~
