摘要
基于灵敏放大器逻辑,采用全定制的方法,设计实现一种AES密码算法的SubByte模块.本文的设计能够实现电路的功耗与运算数据及操作顺序的无关性,从而能够有效地防止差分功耗分析攻击.本设计采用SMIC0.18um CMOS工艺,电路工作频率达到83.3MHz,其版图面积约为0.85mm2.因此,本设计可以广泛应用于高度安全性的对称加密运算设备.
A full-custom design of AES SubByte module based on Sense Amplifier Based Logic is proposed in this paper. The power consumption of this design is independent of both the value and the sequence of the data. Therefore the design is resistant to power analysis attack. This design is implemented using SMIC 0. 18um CMOS technology. Simulation results show that it can work at the frequency of 83.3MHz, and its total area is about 0.85mm^2. This design is suitable for application in the hardware implementation of symmetric-key cryptographic devices that need high security demand.
出处
《小型微型计算机系统》
CSCD
北大核心
2009年第4期737-740,共4页
Journal of Chinese Computer Systems
基金
国家自然科学基金(编号:60576024
60776028)资助
