摘要
AES/Rijndael算法是高性能的加密算法,具有极佳的抗攻击性能。文章提出了AES/Rijndael算法协处理器的半定制ASIC硬件实现方案,设计兼顾了处理速度与硬件资源耗费。其较高的加密强度,对于保护关键信息的安全具有很强的实用价值。方案在Cyclone系列FPGA芯片上实现,占用逻辑单元1400余个,综合仿真和实测的结果验证了本设计的正确性。
The AES/Rijndael algorithm, an encryption algorithm of high performance, has excellent anti-attack performance. This paper presents a half-customed ASIC hardware scheme and an implementation of the AES/Rijndael algorithm coprocessor. The design has made a balance between speed and hardware resources. Its high encryption intensity is valuable in the protection of crucial information security. The design is implemented in Cyclone＇s FPGA, costing 1400 LEs. The scheme has been verified by simulation and experimentation.
出处
《电路与系统学报》
CSCD
北大核心
2007年第4期37-40,共4页
Journal of Circuits and Systems
