期刊文献+

反馈式ECL记忆门的记忆性能和移位计数器 被引量:1

Memory Property of a Feedback ECL Memory-Gate and ECL Shifting Counter
下载PDF
导出
摘要 经过数学论证表明,改进反馈式ECL(MFECL)门可在二个状态中任一态保持稳定,所以认为MFECL门就是一种ECL记忆门或D锁存器.提出了一种由两个ECL记忆门组成的ECL主从D触发器.在上述理论基础上,利用此主从D触发器设计出5进制移位型计数器.经过计算机模拟上述电路,验证了理论和电路的正确性. By mathematical proof,we identify a modified feedback emitter-coupled logic (MFECL) gate with an ECL memory-gate or D latch ,because the MFECL gate is able to keep steady either of two states. Then we present a D master-slave flipflop that consists of two ECL memory-gates. On the basis of the above theory,a five-carry shifting counter ~s designed using such D master-slave flip-flops. The above theory and circuits are verified through computer simulation.
出处 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2006年第12期2184-2189,共6页 半导体学报(英文版)
基金 黑龙江省高校重点实验室基金(批准号:ZDDZ2006-10) 黑龙江省科技攻关计划(批准号:GC02A121)资助项目~~
关键词 反馈式ECL记忆门的记忆性能 D锁存器 主从D触发器 5进制移位型计数器 memory property of feedback ECL memory-gate D latch D master-slave flip-flop five-carry shifting counter
  • 相关文献

参考文献10

二级参考文献33

  • 1吴训威,F.Prosser.数字电路的开关级设计理论[J].中国科学(E辑),1996,26(3):257-265. 被引量:15
  • 2方振贤,刘莹.完整数字电路理论和三值代数[J].电子科学学刊,1996,18(6):612-619. 被引量:7
  • 3Nambu H, Kanetani K, Idei Y. A0.65-ns,72-kb ECL CMOS RAM Macro for a 1-MB SRAM. IEEE Journal of Solid-State Circuits, 1995 ; 30(4) :491 -499. 被引量:1
  • 4Bonges H A, Adams R D, Allen A J, et al. A 576 K 3.5-ns access BiCMOS ECL static RAM with array built-in self-test. IEEE Journal of Solid-State Circuits, 1992;27(4) :649-656. 被引量:1
  • 5Keiidhi Higeta, Masami Usami, Masayuki ohayashi,et al. A soft-error-immune 0. 9-ns 1. 15-Mb ECLCMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry. IEEE Journal of Solid-State Circuits,1996;31(10):1443-1450. 被引量:1
  • 6Elmasry M I. Digital Bipolar Integrated Circuits,New York :John Wiley & Sons, 1983. 被引量:1
  • 7Vojin G Oklobdzija. An ECL gate with improved speed and low power in a BiCMOS process. IEEE J Solid-State Circuits, 1996;31 ( 1 ) : 77 - 83. 被引量:1
  • 8Norman P Jouppi, Stenfanos Sidiropoulos, Suresh Menon. A speed, power and supply noise evaluation of ECL driver circuits. IEEE J Solid-State Circuits,1996 ;31 (1) : 38-45. 被引量:1
  • 9Tseng Yuh-Kuang, Wu Chung-Yu. A 1.5-V differential cross-coupled bootstrapped BiCMOS logic for lowvoltage applications. IEEE J Solid-State Circuits,1998:33(10):1576-1579. 被引量:1
  • 10Seng Y K, Rofuil S S. 1.1 V full-swing double bootstrapped BiCMOS logic gates. IEEE Proc Circuits Devices System, 1996 ; 143 (1) : 41 - 45. 被引量:1

共引文献24

同被引文献6

引证文献1

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部