摘要
通过对计数器和钟控传输门绝热逻辑电路工作原理及结构的研究,提出一种带复位功能的低功耗十进制计数器设计方案.新方案利用CTGAL电路钟控传输门对输入信号进行采样,然后通过自举操作的NMOS管和CMOS-latch结构对输出负载进行全绝热方式充放电,并通过计数器预置复位端结构实现进制可变计数器的设计.PSPICE的模拟结果表明:所设计的电路具有正确的逻辑功能,在相同工作频率下,与传统CMOS电路实现的十进制计数器相比,平均节省能耗约82%.
Based on the working principle,counter structure and Clocked Transmission Gate Adiabatic Logic circuits,a design scheme of decimal counter with reset is proposed.The scheme makes use of clocked transmission gate to sample the input signals,then output loads are charged or discharged in a fully adiabatic manner using bootstrapped NMOS and CMOS-latch structure.The scale alterable counter is implemented by adopting the proposed reset structure.PSPICE simulation results substantiate the validity of the functionality of the designed circuits,which can save up to about 82% energy compared to generic CMOS decimal counter at the same frequency.
出处
《宁波大学学报（理工版）》
CAS
2009年第4期495-499,共5页
Journal of Ningbo University：Natural Science and Engineering Edition
基金
国家自然科学基金(60776022)
浙江省科技计划资助项目(2008C21166)
浙江省科技厅新苗人才计划(2008R40G2070015)
宁波大学教授基金
胡岚优秀博士基金资助项目
浙江省大学生创新创业孵化项目
