摘要
提出了一种在FPGA器件上实现的流水线并行FIR滤波器结构。首先比较了FIR滤波器三种硬件实现所用的资源,然后在理论上推出该流水线并行结构滤波器的实现方法及其可行性,给出了硬件实现模块。实验结果表明,这种改进滤波器结构实现的算法可以灵活地处理综合的面积和速度的约束关系,使设计达到最优。
A parallel pipelined FIR filter implemented in FPGA is presented. Resources needed for 3 different hardware implementations of the FIR filter are compared. Method for implementation of the parallel pipelined filter is derived from theory,and its feasibility is demonstrated. The implemented modules are analyzed and experimental results are provided. Experiments show that the area and speed restrictions of the synthesis can be flexibly optimized by using the improved algorithm of the proposed FIR filter architecture.
出处
《微电子学》
CAS
CSCD
北大核心
2004年第5期582-585,588,共5页
Microelectronics
基金
国家自然科学基金(60272072)
"跨世纪优秀人才"培养计划资助项目(2000年度)
