摘要
提出了一种支持高性能可复用微控制器芯核的体系结构的多路总线及接口,解决了片上外设与微控制器CPU之间的扩展和匹配问题,使得芯核内部互联网络简化,时钟率提高,实现了高性能微控制器的可复用性设计。
In design of the reusable Microcontroller IP core,the communication of the microcontroller and the on-chip peripherals is important to the performance and reusability.The externally accessible Bus stemming from the Special Function Register enables the integration of registers controlling extra on-chip peripherals easy within the SFR address space of microcontroller.The fundamentals learned on this controller should transfer easily to other processors or to more sophisticated architectures.
出处
《计算机工程与应用》
CSCD
北大核心
2005年第2期107-108,132,共3页
Computer Engineering and Applications
基金
航天创新基金资助项目
