摘要
提出一种在FPGA器件上实现流水线并行FIR滤波器结构。首先从理论上分析有限冲激响应(FIR)数字滤波器的特点,并推出利用FPGA器件实现的可行性及其基本结构。接着利用VHDL实现每个模块,并对其进行仿真。
This paper will put forward an architecture of pineline parallel FIR filter implemented on FPGA device. First of all, analyze the characteristic of finite impulse response（FIR） digital filter, and release the method of pineline parallel architecture filter and the basic architecture. Then implement every module with YHDL, and simulation.
出处
《电子技术（上海）》
2009年第1期1-3,共3页
Electronic Technology
