This paper presents area efficient architecture of modulo 2<sup>n </sup>- 3 adder. Modulo adder is one of the main components for the implementation of residue number system (RNS) based applications. The p...This paper presents area efficient architecture of modulo 2<sup>n </sup>- 3 adder. Modulo adder is one of the main components for the implementation of residue number system (RNS) based applications. The proposed modulo 2<sup>n </sup>- 3 adder is implemented effectively, which utilizes parallel prefix and sparse concepts. The carries of some bits are calculated with the help of sparse approach in log<sub>2</sub>n prefix levels. This scheme is implemented with the help of idempotency property of the parallel prefix carry operator and its consistency. Parallel prefix structure contributes to fast carry computation. This will reduce area as well as routing complexity efficiently. The presented adder has double representation of residues in {0, 1, and 2}. The proposed adder offers significant reduction in area as the number of bits increases.展开更多
This paper presents an optimized 64-bit parallel adder, Sparse-tree architecture enames low carry-merge fan-outs and inter-stage wiring complexity. Single-rail and semi-dynamic circuit improves operation speed. Simula...This paper presents an optimized 64-bit parallel adder, Sparse-tree architecture enames low carry-merge fan-outs and inter-stage wiring complexity. Single-rail and semi-dynamic circuit improves operation speed. Simulation results show that the proposed adder can operate at 485ps with power of 25.6mW in 0.18μm CMOS process. It achieves the goal of higher speed and lower power.展开更多
文摘This paper presents area efficient architecture of modulo 2<sup>n </sup>- 3 adder. Modulo adder is one of the main components for the implementation of residue number system (RNS) based applications. The proposed modulo 2<sup>n </sup>- 3 adder is implemented effectively, which utilizes parallel prefix and sparse concepts. The carries of some bits are calculated with the help of sparse approach in log<sub>2</sub>n prefix levels. This scheme is implemented with the help of idempotency property of the parallel prefix carry operator and its consistency. Parallel prefix structure contributes to fast carry computation. This will reduce area as well as routing complexity efficiently. The presented adder has double representation of residues in {0, 1, and 2}. The proposed adder offers significant reduction in area as the number of bits increases.
基金Supported by the National Natural Science Foundation of China under Grant Nos. 60273069, 60376018, 90207011, the National High Technology Development 863 Program of China under Grant No. 2002AAl10020, and the Adwnced Research Foundation of NUDT under Grant No. JC03-06-007.
文摘This paper presents an optimized 64-bit parallel adder, Sparse-tree architecture enames low carry-merge fan-outs and inter-stage wiring complexity. Single-rail and semi-dynamic circuit improves operation speed. Simulation results show that the proposed adder can operate at 485ps with power of 25.6mW in 0.18μm CMOS process. It achieves the goal of higher speed and lower power.
