摘要
针对串行进位加法器存在的延时问题,采用一种基于Sklansky结构的并行前缀加法器,通过对并行前缀加法器各个模块进行优化,设计实现了一个24位并行前缀加法器。通过与24位串行进位加法器进行延时比较,结果表明,Sklansky并行前缀结构的加法器,能有效提高运算速度。
Aiming at the delay problem of serial carry adder（SCA）,a parallel prefix adder（PPA）based on Sklansky was adopted. A 24-bit PPA was designed and realized on the basis of optimizing the various modules of PPA. By comparing the delay of 24-bit PPA with that of 24-bit SCA,the results show that the parallel prefix adder based on Sklansky can increase the computing speed effectively.
出处
《现代电子技术》
北大核心
2015年第21期145-148,共4页
Modern Electronics Technique
基金
国家自然科学基金项目(61274085)
华南理工大学中央高校基本科研学生项目(10561201435)
