This paper presents the design and experimental results of a continuous-time (CT) sigma-delta (ΣΔ) modulator with data-weighted average (DWA) technology for WiMAX applications. The proposed modulator comprises a thi...This paper presents the design and experimental results of a continuous-time (CT) sigma-delta (ΣΔ) modulator with data-weighted average (DWA) technology for WiMAX applications. The proposed modulator comprises a third-order active RC loop filter, internal quantizer operating at 160 MHz and three DAC circuits. A multi-bit quantizer is used to increase resolution and multi-bit non-return-to-zero (NRZ) DACs are adopted to reduce clock jitter sensitivity. The NRZ DAC circuits with quantizer excess loop delay compensation are set to be half the sampling period of the quantizer for increasing modulator stability. A dynamic element matching (DEM) technique is applied to multi-bit ΣΔ modulators to improve the nonlinearity of the internal DAC. This approach translates the harmonic distortion components of a nonideal DAC in the feedback loop of a ΣΔ modulator to high-frequency components. Capacitor tuning is utilized to overcome loop coefficient shifts due to process variations. The DWA technique is used for reducing DAC noise due to component mismatches. The prototype is implemented in TSMC 0.18 um CMOS process. Experimental results show that the ΣΔ modulator achieves 54-dB dynamic range, 51-dB SNR, and 48-dB SNDR over a 10-MHz signal bandwidth with an oversampling ratio (OSR) of 8, while dissipating 19.8 mW from a 1.2-V supply. Including pads, the chip area is 1.156 mm2.展开更多
设计了一种适用于Σ-ΔADC(模数转换器)的低功耗数字抽取滤波器。该数字抽取滤波器采用三级结构实现,分别是CIC滤波器、补偿滤波器和半带滤波器。在设计中,运用Noble恒等式原理、多相分解技术和CSD编码技术,初步降低了滤波器的功耗;根...设计了一种适用于Σ-ΔADC(模数转换器)的低功耗数字抽取滤波器。该数字抽取滤波器采用三级结构实现,分别是CIC滤波器、补偿滤波器和半带滤波器。在设计中,运用Noble恒等式原理、多相分解技术和CSD编码技术,初步降低了滤波器的功耗;根据补偿滤波器和半带滤波器长度的奇偶性和系数的对称性,提出一种奇偶优化法再次优化滤波器结构,进一步降低了整个滤波器的功耗,从而实现低功耗的目的。本设计基于110 nm CMOS工艺,在10MHz采样频率、5 k Hz正弦输入信号频率和256倍降采样率的情况下进行仿真。后仿真结果表明,滤波器的信噪失真比(SNDR)为91.5 d B,无杂散动态范围(SFDR)为97.0 d B,有效位数(ENOB)达到14.91 bit。在1.5 V电源电压下,数字电路(带SPI)的面积约为0.31 mm×0.81 mm,总功耗仅为376μW。展开更多
文摘This paper presents the design and experimental results of a continuous-time (CT) sigma-delta (ΣΔ) modulator with data-weighted average (DWA) technology for WiMAX applications. The proposed modulator comprises a third-order active RC loop filter, internal quantizer operating at 160 MHz and three DAC circuits. A multi-bit quantizer is used to increase resolution and multi-bit non-return-to-zero (NRZ) DACs are adopted to reduce clock jitter sensitivity. The NRZ DAC circuits with quantizer excess loop delay compensation are set to be half the sampling period of the quantizer for increasing modulator stability. A dynamic element matching (DEM) technique is applied to multi-bit ΣΔ modulators to improve the nonlinearity of the internal DAC. This approach translates the harmonic distortion components of a nonideal DAC in the feedback loop of a ΣΔ modulator to high-frequency components. Capacitor tuning is utilized to overcome loop coefficient shifts due to process variations. The DWA technique is used for reducing DAC noise due to component mismatches. The prototype is implemented in TSMC 0.18 um CMOS process. Experimental results show that the ΣΔ modulator achieves 54-dB dynamic range, 51-dB SNR, and 48-dB SNDR over a 10-MHz signal bandwidth with an oversampling ratio (OSR) of 8, while dissipating 19.8 mW from a 1.2-V supply. Including pads, the chip area is 1.156 mm2.
文摘设计了一种适用于Σ-ΔADC(模数转换器)的低功耗数字抽取滤波器。该数字抽取滤波器采用三级结构实现,分别是CIC滤波器、补偿滤波器和半带滤波器。在设计中,运用Noble恒等式原理、多相分解技术和CSD编码技术,初步降低了滤波器的功耗;根据补偿滤波器和半带滤波器长度的奇偶性和系数的对称性,提出一种奇偶优化法再次优化滤波器结构,进一步降低了整个滤波器的功耗,从而实现低功耗的目的。本设计基于110 nm CMOS工艺,在10MHz采样频率、5 k Hz正弦输入信号频率和256倍降采样率的情况下进行仿真。后仿真结果表明,滤波器的信噪失真比(SNDR)为91.5 d B,无杂散动态范围(SFDR)为97.0 d B,有效位数(ENOB)达到14.91 bit。在1.5 V电源电压下,数字电路(带SPI)的面积约为0.31 mm×0.81 mm,总功耗仅为376μW。
