摘要
设计了一种适用于Σ-ΔADC(模数转换器)的低功耗数字抽取滤波器。该数字抽取滤波器采用三级结构实现,分别是CIC滤波器、补偿滤波器和半带滤波器。在设计中,运用Noble恒等式原理、多相分解技术和CSD编码技术,初步降低了滤波器的功耗;根据补偿滤波器和半带滤波器长度的奇偶性和系数的对称性,提出一种奇偶优化法再次优化滤波器结构,进一步降低了整个滤波器的功耗,从而实现低功耗的目的。本设计基于110 nm CMOS工艺,在10MHz采样频率、5 k Hz正弦输入信号频率和256倍降采样率的情况下进行仿真。后仿真结果表明,滤波器的信噪失真比(SNDR)为91.5 d B,无杂散动态范围(SFDR)为97.0 d B,有效位数(ENOB)达到14.91 bit。在1.5 V电源电压下,数字电路(带SPI)的面积约为0.31 mm×0.81 mm,总功耗仅为376μW。
A low-power digital decimation filter for Sigma-Delta ADC was designed. The filter consisted of a CIC filter, a compensation filter and a half-band filter. In the design, the power consumption of the whole filter was reduced by using Noble＇s identity principle, polyphase decomposition technique and CSD encoding technique. According to the parity of the length and the symmetry of the coefficients of the compensation filter and the half-band filter, a parity optimization method was presented to optimize the structure of the filter again. This method could also further reduce the power consumption of the entire filter, therefore, the purpose of low power consumption was achieved. Based on the 110 nm CMOS process, and under the circumstance of 10 MHz sampling frequency, 5 kHz sinusoidal input signal frequency and 256 times down sampling rate, the post simulation results show that the signal-to-noise and distortion ratio（SNDR） of the filter is 91.5 dB, the spurious free dynamic range（SFDR） is 97.0 dB, and the effective number of bits（ENOB） is 14.91 bit. The area of digital circuit （with SPI） is about 0.31 mm×0.81 mm, and the total power consumption is only 376 μW at a power supply of 1.5 V.
出处
《电子元件与材料》
CAS
CSCD
2017年第11期52-59,共8页
Electronic Components And Materials
基金
国家自然科学基金资助(No.61274043)
国家自然科学基金资助((No.62173010)
湖南省自然科学杰出青年基金资助((No.2015 JJ1014)
关键词
Σ-ΔADC
低功耗
数字抽取滤波器
多相分解
系数对称
奇偶优化法
Sigma-Delta ADC
low power
digital decimation filter
polyphase decomposition
coefficient symmetry
parity optimization method
