1STASZEWSKI R B,VEMATAPALLI S,VALLUR P,et al.1.3v 20ps time to digital converter for frequency synthesis in 90nm cmos[J] .IEEE Transations on Circuits,2006,53 (3):220-224. 被引量:1
2HUNG C C,LIU Shenluan.A 40-GHz fast-locked all-digital phaselocked loop using a modified bang-bang algorithm[J] .IEEE Transctions on Circuits And Systems,2011,39 (5):321-326. 被引量:1
4TOKAIRIN T,OKADA M,KITSUNEZAKA M,et al.A 2.1-to-2.8 GHz Low-Phase-Noise All-Digital Fraauercy Synthesizer with a Time-Windowed Time-to-Digital Converter[J] .IEEE Journal of Solid-state Civcuits,2010,45 (12):2852-2590. 被引量:1
5LIU Wei,LI Wei,REN Peng,et al.A PVT Tolerant 10 to 500 MHz All-Digital Phase-Locked Loop With Coupled TDC and DCO[J] .IEEE Journal of Solid-state Circuits,2011,45(2):314-321. 被引量:1
6MANTYNIEMI A,RAHKONEN T,KOSTAMOVAARA J,et al.A cmos time-to-digital converter (TDC) based on a cyclic time domain successive approximation interpolation method[J] .IEEE Journal of Solid-state Circuits,2009,44(11):3067-3078. 被引量:1
7EFFENDRIK P,JIANG Wenlong,VAN DE GEVEL M,et al.Timeto-digital converter (TDC) for wimax adpll in 40 nm cmos[C] //IEEE European Conference on Circuit Theory and Design.2011:365-369. 被引量:1
8THOMAS O,PETER N.A digitally controlled pll for SoC applications[J] .IEEE Journal of Solid-state Circuits,2004,39 (5):751. 被引量:1
9TOKAIRIN T, OKADA M, KITSUNEZUKA M, et al. A 2.1-to-2.8-OHz low-phase-noise all-digital frequency synthesizer with a time-windowed time-to-digital converter[J]. IEEE J Solid-State Circ.its, 2010,45(12) : 2582-2590. 被引量:1
10DU L, WU S, JIANG M, et al. A 10-bit 100 MS/s subrange SAR AI with time-domain quantization [C]//ISCAS, Melbourne, Australia: IEEE Press, 2014: 301-304. 被引量:1