摘要
针对不同状态机的状态分配及功能输出不同,提出一种归一化的系统设计方法,通过中规模集成器件设计状态机中组合逻辑部分,集成计数器设计时序逻辑部分,设计过程清晰且可移植性高。并以四进制加法计数器和减法计数器为例,详细阐述了设计方法,通过QuartusⅡ软件进行了仿真和实测实验。研究结果显示,采用系统化设计方法的结果与采用传统触发器方法设计的结果完全一致,从而验证了该方法的有效性。
Aiming at the difference of state allocation and function output of different state machines,a normalized system design method is proposed,which designs the combined logic part of the state machine through the medium scale integration device and the timing logic part through the integration counter.The design process is clear and portable.Different state machines can be configured with different parameters.In quaternary and subtract counter,this paper expounds the design method,and through the QuartusⅡsoftware are simulated and the measured experiment.The results show that the results of the systematic design method are completely consistent with those of the traditional trigger design.
作者
石惠敏
方振国
陈建国
董坤
胡锋
SHI Hui-min;FANG Zhen-guo;CHEN Jian-guo;DONG Kun;HU Feng(School of Physics and Electric Information,Huaibei Normal University,Huaibei 235000,China)
出处
《长春师范大学学报》
2019年第12期24-29,共6页
Journal of Changchun Normal University
基金
安徽省质量工程项目“通信工程专业综合改革试点”(2016zy109)
安徽省质量工程项目“新工科背景下多学科交叉的创新人才培养模式探索与实践”(2017jyxm0210)
安徽省质量工程项目“电子信息工程省级示范教研室”(2018jyssf036)
