摘要
本文研究了用Verilog实现有限状态机的各种不同的编码方式和描述风格,并从综合、毛刺、面积、速度这几方面研究了不同实现方式的利弊。最后,以SoC芯片中DMAArbitor有限状态机为例,我们用DesignComplier(DC)对七种设计进行了综合,并分析了综合后的面积和时延信息。
This paper studies different state encoding styles and Verilog descriptions of Finite State Machine (FSM). Based on these styles, benefits and shortages are described. Furthermore, as a FSM design example, a DMA Arbiter is presented and implemented in seven ways discussed in this paper. The timing and area results of Design Compiler synthesis are also analyzed.
出处
《微电子学与计算机》
CSCD
北大核心
2004年第11期146-148,157,共4页
Microelectronics & Computer
基金
国家863计划资助(2003AA1Z1350)
