摘要
提出一种基于CMOS技术的静态双沿顺序脉冲发生器结构。他是由以基于CMOS二选一选择器的电平型触发器构成的记忆单元和一个与门阵列组成的转译单元构成的。与门阵列的转译单元使顺序脉冲发生器在时钟上升沿和下降沿处均能输出移位脉冲,从而形成双沿触发的功能。仿真验证其功能正确,且根据分析该结构不仅能够节省芯片面积,还可以大大减小芯片的功耗。
This paper presents a CMOS static double- edge- triggered sequential- pulse- generator. The novel design involves a memorizing unit on the basis of CMOS level - triggers and a unit of an AND gates array. This array of AND gates can make the sequential - pulse - generator output sequential - pulse at both rising and falling edge. The simulation results have demonstrated that this SPG has ideal logic functionality,lower power dissipation and less area.
出处
《现代电子技术》
2006年第8期22-23,29,共3页
Modern Electronics Technique
关键词
CMOS
双沿顺序脉冲发生器
功耗
与门阵列
CMOS
double - edge - triggered sequential - pulse - generator
power dissipation
gate array
