摘要
分频器是数字系统设计中最常见的单元电路,对高稳定和准确的基准时钟源进行不同倍数的分频,以得到同样稳定和准确的信号,为各模块提供所需的时钟频率。介绍了一种分数分频器的实现方法,该分频器能对时钟源信号进行任意分数或小数倍分频,给出了该方法的设计原理及实现的Verilog代码,并利用QuartusⅡ软件进行了仿真,仿真波形与硬件结果都验证了设计的正确性。该方法结构简单,可避免出现竞争冒险和毛刺问题,并且修改方便,具有很好的可移植性,对任何分频器的设计都具有一定的借鉴意义。
Frequency divider is a common unit circuit in digital system. The high stable and accurate signal is divided into different frequency signal with the same stability and curacy that provides the required clock frequency for each module. A realization method of arbitrary fraction or decimal fraction frequency division is presented. The principle of the design and the code based on Verilog are also presented,and their functions are simulated using Quartus. The simulation waveforms and hardware results verify the correctness of the design. This method is simple and can avoid competition risks and burr. The design method can also be easily modified and has good portability,so it has reference for the design of any arbitrary frequency divider.
作者
任青莲
李东红
Ren Qinglian Li Donghong(College of Information Engineering, Taiyuan University of Science and Technology, Taiyuan Shanxi 030024, China College of Information Engineering, Huake University, Taiyuan Shanxi 030024, China)
出处
《山西电子技术》
2016年第5期20-22,共3页
Shanxi Electronic Technology
基金
山西省2014年教育教学改革研究项目(J2014152)
