摘要
基于整数和小数分频的实现原理,提出了整数和小数分频器的算法和结构,采用Verilog硬件描述语言优化设计了偶数、非50%占空比和50%占空比的奇数、半整数分频器,重点对任意小数分频器进行了设计优化.用LDV5.1进行了仿真,用Synplify Pro进行了基于ALTERA公司FPGA的综合,证明了其可行性.
This paper presents the algorithm, structure and Verilog implementation of integer and decimal frequency dividers, including types of even integer, odd integer with duty cycle 50% and not exactly 50%, N-0.5 and random decimal. Based on the FPGA device of ALTERA, they are simulated with LDV5.1, and synthsized with Synplify Pro.
出处
《河南大学学报（自然科学版）》
CAS
北大核心
2007年第4期343-346,共4页
Journal of Henan University:Natural Science
基金
河南省高校创新人才培养工程资助课题
