摘要
采用易于FPGA实现的归一化最小和算法,通过选取合适的归一化因子,将乘法转化成移位和加法运算。在高斯白噪声信道下,仿真该译码算法得出最佳的译码迭代次数,并结合Xilinx XC7VX485T资源确定量化位数。然后基于该算法和这3个参数设计了一种全新的、高速部分并行的DSC译码器。该译码器最大限度地实现了译码效率、译码复杂度、FPGA资源利用率之间的平衡,并在Xilinx XC7VX485T芯片上实现了该译码器,其吞吐率可达197 Mb/s。
The algorithm is adopted and implemented on FPGA, whose name is Normalized min- sum algorithm, multiplication of the algorithm could be converted into shift and addition operation, through selecting the suitable normalized factor. The optimal decoding iteration number could be obtained, through simulating the algorithm in Additive White Gaussian Noise channel. Besides, the quanti-zation bits could be determined through simulating and resource of Xilinx XC7VX485 T. Then a DSC decoder which is new and high- speed and partly parallel could be designed based on the algorithm and three parameters. The decoder extremely realizes the balance of decoding efficiency, decoding complexity and the utilization of FPGA resource. And the decoder has been realized on Xil-inx XC7VX485 T chip, whose throughput rate could up to 197 Mb / s.
出处
《电子技术应用》
北大核心
2016年第9期39-43,共5页
Application of Electronic Technique
