摘要
为了满足片上系统对模数转换器的低功耗和高性能的要求,设计并实现了一种1.2V7位125MS/s双采样流水线模数转换器.该模数转换器采用了一种新的运算放大器共享技术以及相应的时序关系,从而消除了采样时序失配问题,并减小了整个模数转换器的功耗和面积.该模数转换器采用0.13μm CMOS工艺实现,测试结果表明,该模数转换器的最大信噪失真比为43.38dB,有效位数为6.8位.在电源电压为1.2V、采样速率为125MS/s时,该模数转换器的功耗仅为10.8mW.
A 7 bit 125 MS/s double sample pipelined ADC which can achieve a low power and a high performance for the SoC system is presented. The presented ADC with op-amp sharing between two channels and a new timing scheme can not only eliminate sampling timing skew, but also has a low power and a small area. Test results show that the ADC designed in a 0.13μm CMOS process achieves a maximum SNDR of 43.38 dB, and that ENOB is 6.8 bits. The ADC consumes 10.8 mW at 125 MS/s under a 1.2 V supply voltage.
出处
《西安电子科技大学学报》
EI
CAS
CSCD
北大核心
2016年第4期23-28,共6页
Journal of Xidian University
基金
国家自然科学基金资助项目(61204085
61334002)
关键词
双采样
运放共享
时间交织
流水线型模数转换器
double sample
op-amp sharing
time-interleaved
pipelined analog to digital converter
