摘要
基于"运放共享"电路工作原理,研究了流水线A/D转换器的MDAC模块因采用"运放共享"结构引入的"记忆效应";搭建实际电路,测试出"记忆效应"因子;采用Matlab,仿真了此效应对12位100 MHz流水线A/D转换器各项指标的影响。提出了一种基于FIR数字滤波器的校正算法,在数字域校正模拟电路中由于电容的非理想因素导致的误差。输入为1 MHz正弦波信号时,仿真结果表明,经过数字后台校正后,SFDR为91 dB,SNR为71 dB,流水线A/D转换器系统的指标有了大幅度的提升。
Based on the theory of op-arnp sharing technique, memory effects arisen from MDAC with op-arnp sharing structure in pipelined A/D converter were studied. An exemplary method was provided to get the memory parameter, and the influence of memory effect on the 12-bit 100 MS/s pipelined A/D converter was also investigated. A calibration algorithm based on FIR filter was proposed, which could correct the error resulted from analog components in digital domain. With a 1MHz sinusoidal input, test results showed that the pipelined A/D converter had an SFDR of 91 dB and an SNR of 71 dB. Performance of the pipelined A/D converter was greatly improved after calibration.
出处
《微电子学》
CAS
CSCD
北大核心
2008年第2期201-205,共5页
Microelectronics
