摘要
针对传统模数转换器(analog to digital convertor,ADC)设计复杂度高、仿真迭代时间长的问题,提出了一种高精度ADC系统设计与建模方法。该方法以10 bit 50 MHz流水线ADC为例,首先选取分离采样架构,进行电路的s域变换理论分析;其次对电路中各种非理想噪声的表达式进行精确推导,根据系统中的运放功耗指标进行参数优化;最后分别在MATLAB和Cadence软件中建立模型,进行100点蒙特卡洛仿真。仿真结果表明,在TSMC 180 nm工艺失配下,该流水线ADC有效位数达到9.70 bit,无杂散动态范围维持在76 dB附近,微分非线性在0.3 LSB以内,积分非线性在0.5 LSB以内,核心功耗在8 mW,该分析方法在保证流水线ADC优异性能的同时,大幅提高了设计效率。
A high-precision ADC system design and modeling method is proposed to address the high design complexity and long simulation iteration time issues of traditional analog to digital converter(ADC).This method takes a 10 bit 50 MHz pipeline ADC as an example.Firstly,a separate sampling architecture is selected for the s-domain transformation theory analysis of the circuit.Secondly,the expressions of various non ideal noise in the circuit are accurately derived,and parameter optimization is carried out based on the operational amplifier power consumption indicators in the system.Finally,models were established in MATLAB and Cadence software for 100 points Monte Carlo simulation.The simulation results showed that under the TSMC 180 nm process mismatch,the effective bit of the pipeline ADC reached 9.70 bit,the spurious free dynamic range was maintained around 76 dB,the differential nonlinearity was within 0.3 LSB,the integral nonlinearity was within 0.5 LSB,and the core power consumption was 8 mW.This analysis method not only ensures the excellent performance of the pipeline ADC,but also,Significantly improved design efficiency.
作者
张华盛
宋树祥
蔡超波
Zhang Huasheng;Song Shuxiang;Cai Chaobo(School of Electronic and Engineering/School of Integrated Circuits,Guangxi Normal University,Guilin 541004,China;Key Laboratory of Integrated Circuits and Microsystems(Guangxi Normal University),Education Department of Guangxi Zhuang Autonomous Region,Guilin 541004,China)
出处
《国外电子测量技术》
2024年第3期98-105,共8页
Foreign Electronic Measurement Technology
基金
国家自然科学基金(62061005)
广西自然科学基金(2022GXNSFBA035646)
广西创新驱动发展专项(AA19254001)资助。
