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基于VIRTEX架构的FPGA布线资源测试技术

The Research of FPGA Routing Resources Testing Technology Based on VIRTEX Architecture
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摘要 FPGA内部可编程布线资源所占的晶体管数量是所有模块中最多的,其故障发生率也最高,因此布线资源的测试是一个重要的研究领域,也是FPGA测试中的一个难点。通过对基于VIRTEX架构的FPGA布线资源的六长线、长线、单长线的测试技术研究,采用通用方法的组合进行测试,测试程序可读性好、可复用性高,实现了对布线资源测试故障覆盖率高、故障定位准确。 The number of transistors in programmable routing resources inside FPGA shares the most of all modules and the failure rate is the highest, so the test of routing resources is an important area of research and a difficulty in FPGA testing. The paper studies on six long, long, single long line testing of FPGA routing resources technology based on VIRTEX architecture, using the combination of general methods for testing. The realization of routing resources to test faulty coverage is high, and the fault location is accurate, test procedures can be high readability and reusability.
出处 《电子与封装》 2015年第11期17-20,共4页 Electronics & Packaging
关键词 FPGA 布线资源 VIRTEX架构 通用方法组合 FPGA routing resources VIRTEX architecture common methods combination
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  • 1Metra C et al. Novel technique for testing FPGA. Design, Automation and Test in Europe, Palais des Congres Paris, France,1998, pp,89-94. 被引量:1
  • 2Alderighi M, Gummati E, Piuri V, Sechi G. A FPGA based implementation of a fault tolerant neural architecture for photon identification. In Proc. the Int. Symp. Field-Programmable Gate Arrays, Monterey, CA, USA, 1997, pp.166-172. 被引量:1
  • 3Renovell M, Figueras Jl Zorian Y. Test of RAM-based FPGA: Methodology and application to the interconnect. In Proc,15th VLSI Test Sy,p., Anaheim, USA, 1997, pp,230-237. 被引量:1
  • 4Stroud C, Wijesuriya S, Hamilton C, Abramovici M. Built-in self-test of FPGA interconnect. In Proc. the IEEE Int. Test Conf., Washington DC, USA, 1998, pp.404-411. 被引量:1
  • 5Sun X, Xu J, Trouborst P. Testing Xilinx XC4000 configurable logic blocks with carry logic modules. In Proc. the IEEE Int. Syrnp, Defect and Fault Tolerance in VLSI Systems, San Francisco, CA, USA, October 2001,pp.221-229. 被引量:1
  • 6Renovell M, Portal J M, Figueras J, Zorian Y. RAM-based FPGAs: A test approach for the configurable logic. In Proc. the Design, Automation and Test in Europe, Palals des Congres Paris, France, 1998, pp,82-88. 被引量:1
  • 7Huang W K, Meyer F J, Park N, Lombardi F. Testing memory modules in SRAM-based configurable FPGAs. In Proc. IEEE International Workshop on Memory Technology, Design and Test, San Jose, CA, USA, August 1997, pp.79-86. 被引量:1
  • 8Renovell M, SRAM-based FPGAs: A structural test approach. IEEE Ⅺ Brazilian Symposium on Integrated Circuit Design, Rio de Janeiro, Brazil, Oct, 1998, pp.67-72. 被引量:1
  • 9Inoue T et al. Universal test complexity of field programmable gate arrays. In Proc. Asian Test Symp., Bangalore, India,1995, pp.259-265. 被引量:1
  • 10Stroud C et al. Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!). In Proc. VLSI Test Symp., Princeton, N J, USA, 1996, pp.387-392. 被引量:1

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