摘要
针对传统的基于纯硬件平台的FPGA芯片测试方法所存在的种种问题,提出并验证了一种基于软硬件协同技术的FPGA芯片测试方法。该方法引入了软件的灵活性与可观测性等软件技术优势,具有存储深度大、可测I/O管脚数目多、自动完成配置下载(不需人工干预)和自动定位FPGA中的错误等优点,提高了FPGA的测试速度和可靠性,并降低了测试成本,与传统的自动测试仪(ATE)相比有较高的性价比。采用软硬件协同方式针对Xilinx4010的I/O单元进行了测试,实现了对FPGA芯片的自动反复配置、测试和错误定位。
Traditional field programmable gate array （FPGA） test schemes confront many problems, such as memory depth not large enough to meet requirement of configuration of many times, I/O pin counts usually less than needed, manual configuration generation and download, no position of fault sites, etc. A new approach to test FPGA based on SoC HW/SW co-verification technology is proposed and verified in the paper. This test scheme has taken advantage of flexibility and observability of software in conjunction with high-speed simulation of hardware. As a result, efficiency and reliability of the test can be enhanced without manual work. In the experiment, the proposed test approach has been applied to a Xilinx 4010 FPGA to implement automatic configuration, test as well as location of fault sites.
出处
《电子科技大学学报》
EI
CAS
CSCD
北大核心
2009年第5期716-720,共5页
Journal of University of Electronic Science and Technology of China
基金
部级预研基金
