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基于硬环境的动态FPGA测试平台架构设计 被引量:1

Dynamic FPGA Test Platform Architecture Design Based On Hardware Environment
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摘要 FPGA在可编程嵌入式系统领域起到了至关重要的作用。FPGA不仅内部结构复杂,而且随着电路集成规模和管脚规模的日渐剧增,针对FPGA的测试的难度逐渐加大。在分析和比较主流测试方法的基础上,结合实际项目中的设计,介绍了基于硬环境的FPGA测试平台的整体架构和各模块的功能,突出测试平台的动态性和测试的完备性。 FPGA has been playing a crucial role in the field of programmable embedded systems. It not only has a complex inter- nal structure,the difficulty of the professional test for FPGA the gradual increases with increasingly sharp increase of the integrated circuit size and pin-scale source.On the basis of the analysis and comparison of the mainstream test method,combined with design in the actual project ,The overall architecture and the function of each module are elaborated for FPGA test in hard platform environment ,highlighting the dynamic nature of the test platform and test completeness at the same time.
出处 《电脑知识与技术》 2013年第1期198-199,218,共3页 Computer Knowledge and Technology
关键词 FPGA 测试平台 架构 动态性 完备性 FPGA test platform architecture dynamic completeness
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  • 1唐恒标,冯建华,冯建科.基于测试系统的FPGA逻辑资源的测试[J].微电子学,2006,36(3):292-295. 被引量:13
  • 2杨硕,张海滨,宋文涛.通用FPGA算法测试平台[J].微计算机信息,2006,22(07Z):219-221. 被引量:3
  • 3Huang W K, Meyer F J, Lombardi F. An approach for detecting multiple faulty FPGA logic block. IEEE Trans Computers, 2000, 49(1): 48-54 被引量:1
  • 4Gao H X, Yang Y T, Ma X H, et al. Testing for resistive shorts in FPGA interconnects // Proc IEEE Int Syrup on Quality Electronic Design. San Jose, 2005:159-163 被引量:1
  • 5Vemula S, Stroud C. BIST for I/O buffers in FPGAs//Proc IEEE North Atlantic Test Workshop. Essex Junction, USA, 2005 : 31-36 被引量:1
  • 6Xilinx. EasyPath FPGAs [ EB/OL]. (2006) [2007-09-20] http ://www. xilinx.com/easypath 被引量:1
  • 7Kwiat K, Debanv W, Hariri S. Effects of technology mapping on fault-detection coverage in reprogrammable FPGA's. IEE Proc Comp Digi Tech, 1995, 142(6): 407- 410 被引量:1
  • 8Renovell M, Portal J M, Faure P, et al. TOF: A tool for test pattern generation optimization of an FPGA application oriented test//Proc IEEE Asian Test Symp. Taibei, 2000, 323-328 被引量:1
  • 9Renovell M, Faure P, Portal J M, et al. IS-FPGA: A new symmetric FPGA architecture with implicit SCAN // Proc IEEE Int Test Conf. Baltimore, USA, 2001, 924-931 被引量:1
  • 10Rebaudengo M, Reorda M S, Violante M. A new functional fault model for FPGA Application-Oriented testing // Proc IEEE Int Symp on DFT. Vancouver, 2002:372-380 被引量:1

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