摘要
为了满足So C系统对低功耗和高性能模数转换器ADC的需求,文中设计了一种双采样1.2 V 7位125 Mb/s流水线模数转换器。该双采样流水线模数转换器是由两个转换通道组成,两个转换通道之间采用时钟交织技术。为了减小整个模数转换器的功耗和面积,同时消除采样时序失配问题,文中提出了一种在两个通道之间共用运算放大器的电路结构以及相应的工作时序关系。该模数转换器采用0.13-μm CMOS 1p8m工艺实现。仿真结果表明,该模数转换器的最大SNDR为43.38 d B,有效位数ENOB为6.8位。在电源电压为1.2 V,采样速率为125 Mb/s时,该模数转换器的功耗为10.8 m W。
A 7 bits 125 Mb/s double sample pipelined ADC which can achieve low power and high performance for SoC system is presen- ted. The double sampling pipelined ADC is consisted of two conversion channel, the clock mixed technology is used between two conver- sion channel. In order to reduce power consumption and area of the entire ADC, eliminate the sampling timing mismatch problems at the same time, put forward an operational amplifier circuit structure and the corresponding work timing relationships shared between the two channels. Simulation results show that the ADC designed in a 0.13-μm CMOS process achieves a maximum SNDR of 43.38 dB, and ENOB is 6.8 bits. The ADC consumes 10.8 mW at 125 Mb/s under a 1.2-V supply voltage.
出处
《计算机技术与发展》
2015年第7期206-208,共3页
Computer Technology and Development
基金
"十二五"微电子预研(51308010601
51308010711)
总装预研基金(9140A08010712HK6101)
