摘要
提出了锁相环的核心部件压控振荡器(VCO)的一种设计方案.该压控振荡器采用全差分环形压控振荡器结构,其延迟单元使用交叉耦合晶体管对来进行频率调节.基于SMIC0.18μmCMOS工艺,用Hspice对电路进行了仿真.仿真结果表明,该压控振荡器具有良好的线性度,较宽的线性范围以及高的工作频率,在1.8V的低电源电压下,振荡频率的变化范围为402～873MHz,中心频率在635MHz,功耗仅为6mW,振荡在中心频率635MHz时的均方根抖动为3.91ps.
A design project of voltage-controlled oscillator（VOD） which is the central component of the low voltage phase- locked loop（PLL） is proposed in this paper. The VOD adopted the configuration of the full differential voltage-controlled- oscillator and the cross-coupled transistors are used in the delay cells to adjust the frequency. Under the SMIC 0.18μm CMOS model, simulation results in Cadence Hspice indicate that the V（X） proposed behaves in good linearity, wide linear range and high operating frequency. Under a voltage supply of 1.8V, the variety of the frequency is from 402MHz to 873MHz, with the power dissipation of 6mW and rms jitter of 3.91ps at the central frequency of 635MHz.
出处
《微电子学与计算机》
CSCD
北大核心
2008年第5期69-72,共4页
Microelectronics & Computer
