摘要
介绍一种能兼容高速总线AHB的存储控制器结构,其充分利用AMBA2.0协议对高速总线通信方式的规定,实现了对外部RAM和ROM的高效访问控制。该控制器结构在完成总线端和存储端时序转换的基础上,对系统访问中的获取指令、写操作及原子操作进行了优化设计,提高了此类操作的访问效率。此外,本设计采用异步时钟域的设计方法,降低了控制器在空闲状态下的动态功耗。该IP采用硬件描述语言设计,核心部件采用有限状态机实现,最终形成可复用的IP软核。
The paper presents a memory controller IP core based on high-speed bus. It takes full advantage ofthe protocol of AMBA 2. 0 to achieve efficient access to the external RAM and ROM. With the implement of timingtransition between bus-end and memory-end, the memory controller realizes the timing optimization for three specialoperations instruction feteh write access and atomic operation, improving the access efficiency for those behav-iors. Additionally, this design adopts an asynchronous design method for the whole circuit, which reduces the powerof controller under the idle state. This IP is described by VHDL, whose hardeore is implemented with FSM （ FiniteState Machine） , thus forming a reusable soft core.
出处
《电子科技》
2015年第3期99-102,107,共5页
Electronic Science and Technology
关键词
存储控制器
原子操作
低功耗
AHB
memory controller
atomic operation
low power
