3[1]《Avalon Memory Mapped Interface Specification》2006.10 Altera Corporation 被引量:1
4[2]《Avalon Streaming Interface specification》2006.10 Altera Corporation 被引量:1
5[3]《Avalon Interface Specification Reference Manual》2004.9 Altera Corporation 被引量:1
6[4]《Avalon Bus Specification Reference Manual》2003.7 Altera Corporation 被引量:1
7[5]《Quartus Ⅱ Version 7.1HandBook》Volume 4:SOPC Builder 2007.5 Altera Corporation 被引量:1
8A. Rincon, W. Lee and M. Slatery. The Changing Landscape of System - on - Chip Design [ R ]. IBM MicroNews,3rd Quarter 1999, Vol. 5, No. 3, IBM Microelectronics. 被引量:1
9Sudeep Pasricha, Mohamed Ben -Romdhane and Nikil Dutt. High Level Design Space Exploration of Shared Bus Communication Architecture[ R ].CECS Technical Report #04 - 06, University of California, Irvine CA 92697,Mar 13,2004. 被引量:1
10IBM Corp. The CoreConnect Bus Architecture[EB/OL].http ://www - 306. ibm. com/chips/techlib/techlib.nsf/productfamilies/CoreConnect Bus_Architecture. 被引量:1