摘要
采用后台校正技术,通过对级间余量放大器传输函数建模来估计误差,以提高流水线型ADC(analog to digital converter,ADC)的性能。为了在校正精度、硬件消耗、功率消耗和算法收敛速度之间做一个合理的权衡,需要在建模时选用一个合理的插值算法。以一个12位,采样频率40兆的流水线型ADC为原型,分别采用分段线性插值、三次多项式插值对第一级余量放大器传输函数建模,用硬件描述语言Verilog对系统进行描述,结合模拟电路部分进行混合仿真验证,运用综合工具对两种算法对应的Verilog程序进行综合估计。仿真结果表明:两种算法中,分段线性插值法硬件消耗和功耗更低,而多项式插值法校正精度更高,算法收敛更快。
In the background calibration, the residual amplifier transfer function modeling was applied to estimate the errors for improving the performance of pipeline analog to digital converter （ADC）.To find a compromise among cali-bration resolution, hardware consumption, power consumption and the convergence time, an interpolation algorithm was needed to be chosen.Using a 12 bits 40 M sample rate pipeline ADC as prototype, the piecewise linear and cubic poly-nomial were respectively used to model the first stage inter-stage amplifier transfer function.The model was described by verilog, and the analog-digital mixed simulation was put forth by the analog circuit.The code was synthesized to estimate the overhead of the two algorithms.Simulation results showed that piecewise linear interpolation consumered less hardware and power consumption between these two algorithms, while the cubic polynomial interpolation was more precise and convergences faster.
出处
《山东大学学报（工学版）》
CAS
北大核心
2014年第3期41-47,共7页
Journal of Shandong University（Engineering Science）
