摘要
异步采样率转换是连接设备对采样数据独立处理的基础,设备接口之间采用异步采样率转换可有效去除连接设备之间时钟同步锁定的要求。本文先对采样信号特征进行分析,详细讨论了异步采样率转换的相关原理,给出误差分析。文中指出全数字高性能设计实现的两个难点:精确的相位与巨大的系数存储量,并针对这两个问题提出相应解决方法:数字锁相环与系数多项式插值。文章在分析传统多项式插值的基础上,根据CIC低通滤波特性,提出一种新的多项式系数插值生成方法,仿真结果表明,三次多项式插值在不增加运算量的情况下镜像抑制比提高16 dB左右。最后给出基于FPGA的异步采样率转换实现。
Asynchronous sample rate convert （ASRC） is the bedrock for processing the sample data between connected equipments independently. ASRC between the equipment interfaces can avoid the requirement of the clock synchronous lock between connected equipments. Characteristics of sample signal are analyzed, the theory about ASRC is discussed, and the error analysis is given also. Two difficulties, i.e. phase-precise and gigantic coefficient storage are presented. So digital phase-locked loop and the interpolation of the coefficient polynomial are provided. Based on the analysis of the traditional interpolation polynomial and according to the characteristics of the CIC low-pass filtering, a new method of polynomial coefficient interpolation is given. Simulation results show that without operand addition, the cubical polynomial interpolation can provide extra 16 dB gain to the mirrored-restraining rate. Finally, the realization of ASRC is given based on FPGA.
出处
《数据采集与处理》
CSCD
北大核心
2008年第B09期185-189,共5页
Journal of Data Acquisition and Processing
基金
教育部"新世纪优秀人才支持计划"(NCET-04-0209)资助项目
